Address translation in a virtually segmented memory system requires translating a process scoped effective address' segment number (ESID) into a system wide unique virtual segment identifier (VSID). This ESID to VSID mapping is generally provided to the processor via a segment look-aside buffer (SLB) cache located in processor itself. The SLB size is typically small since space on a processor is limited. As a result, workloads with a large number of segments require frequent SLB reloading.
SLB entries (SLBEs) are loaded from in-memory segment tables (STABs) maintained by the operating system for each running process. The SLB can either be software managed by the operating system or hardware managed by the processor.
Software management of the SLB (SSLB) involves the CPU sending an SLB miss interrupt to the operating system, which then uses an interrupt handler to find or create the STAB entry (STE) containing the appropriate ESID to VSID translation information and copy it into an SLBE. SSLB allows the operating system the flexibility to choose which SLBEs get replaced. However, the SLB miss interrupt handler can take tens to hundreds of cycles to complete.
Hardware management of the SLB (HSLB) significantly reduces the SLB replacement overhead because the CPU can directly copy the STE information into an SLBE without having to send an interrupt to the operating system unless the STE needs to be created. CPU access to the STAB can either use physical or virtual addressing. Although physical addressing is easier for the processor, it imposes some limitations on the operating system's ability to optimally manage the STAB's underlying memory.
Virtually addressing the STAB removes those limitations since the operating system is free to do things such as optimizing the STAB's memory affinity by moving it to physical memory closer to the processor that's using it. However, it introduces a new problem since the CPU will now need a hardware page table (HPT) entry (PTE) that translates the STE's virtual address into a physical address. If the PTE doesn't yet exist or has been evicted to make room for other PTEs, the CPU must send a PTE miss interrupt to the operating system requesting that PTE be reloaded. The PTE reload interrupt handler code and the internal translation tables are also accessed virtually, so the PTE reload handler may reference code/data virtual addresses whose STEs also do not have a PTE, and that will cause the CPU running the PTE reload handler to recursively send another PTE miss interrupt potentially leading to an infinite loop.
A simple solution to that circular dependency is to pin all PTEs for every process' STAB so that they cannot be evicted from the HPT. However, this solution also creates new problems. Since every pinned PTE reduces the number of a replaceable PTEs in the HPT, it is possible that may create an HPT thrashing environment where system and workload processes spend more and more of their execution time reloading their replaceable PTEs. In addition, inverted HPTs implemented as n-way associative caches could find one or more associative PTE groups (PTEGs) completely filled by pinned PTEs, and subsequent memory references that need to add a PTE to that group will deadlock because they cannot evict the pinned PTEs.